bcm8021 ? 10 - gbe xaui? transceiver with high-speed redundancy xaui serdes application diagram ? 10-gbe transceiver supporting various operating modes ? ieee 802.3?ae-compliant xaui? to xgmii transceiver ? xaui-to-xaui retiming ? low power dissipation ? less than 300 mw per transceiver channel including i/o ? sonet/sdh-quality jitter performance ? less than three picoseconds rms jitter generation ? exceeds sonet jitter tolerance mask ? high performance programmable receive equalization and transmit pre-emphasis ? transmit pre-emphasis for interoperability with cml serdes ? receive equalization for copper interconnects ? enhanced test capability ? full loopback and on-chip prbs generator/checker ? ieee (1149.1) jtag ? compact 21-mm 21-mm bga package ? no requirement for heat sink or airflow ? advanced 0.13 cmos process technology provides unparalleled performance while achieving the lowest possible power consumption ? ieee 802.3ae 10-gbe physical coding sublayer (pcs) has a selectable 8b/10b encoding/decoding block on-chip that can be configured to support the 10-gbps attachment unit interface (xaui) ? superior jitter characteristics enable the serializing/ deserializing (serdes) of data signals transmitted through front panel or backplane networking equipment supporting both primary and protection circuits ? drive pmd devices or backplane directly with no external clean-up circuit required ? simplifies manufacturability with integrated built-in self-test (bist), high-speed and low-speed loopbacks, and programmable prbs generator/checker ? decreases complexity and reduces board space on multichannel linecard designs features summary of benefits ? 1-gbe and 10-gbe lan, man, wan switches and routers ? advanced test equipment (ate) applications applications
overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2006 by broadcom corporation. all rights reserved. 8021-pb04-r 04/14/06 broadcom ? , the pulse logo, connecting everything ? , and the connecting everything logo are among the trademarks of broadcom corporation and/or its aff iliates in the united states, certain other countries and/or the eu. any other trademarks or trade name s mentioned are the property of their respective owners. bcm8021 block diagram the bcm8021 device integrates xaui serializer/deserializer (serdes) channels leveraging broadcom?s high-performance mixed-signal design experience along with advanced 0.13 cmos process technology. this, combined this with a robust architecture offering the highest degree of flexibility, results is a highly programmable, lowest power serdes solution for network line-card and backplane applications. an internal mux connects the parallel and serial ports to enable fully redundant operation. the mux enables an active serial link to be switched to the parallel interface, while a protection serial link can be continuously monitored to insure its condition. if the active link fails, the protection link can be muxed over through external control to the parallel interface. on the parallel side of the device, transmitters and receivers interface with a 32-bit wide data (xgmii) along with the clock and control signals. the low-speed i/o supports hstl (1.5v or 1.8v) or sstl_2 (2.5v) interfaces. on the serial side of the device, transmitters and receivers support xaui serial transmission rates. an on-chi p phase lock loop (pll) synthesizes the supplied reference clock to support the desired transmit rate, while vlock and data recovery (cdr) units recover the receive rate clock for timing. for high-speed serial copper connections, the device incorporates both transmit pre-emphasis on the transmit channels and receive equalization on the receive channels. transmit pre-emphasis is programmable to improve the overall cable reach and compensate for electrical imperfections associated with traces and connectors. receive equalization provides optimal performance over a variety of receive interfaces. highly programmable test capabilities exist within the device to support high-speed and low-speed loopback using generators/checkers that support prbs 27 to 231 patterns along with ieee802.3ae-defined test patterns. a complete evaluation kit, including an evaluation board, related software, and documentation is available upon request.
|
